RISC-V Prozessor Core for Functional Safety

RISC-V is an open instruction set architecture (ISA) based on the design principle Reduced Instruction Set Computer (RISC). The greatest strengths of the architecture are the modularity of the standard instruction set extensions and along with the possibility of developing very application-specific, high-performance and energy-efficient processors. The Fraunhofer IPMS whitepaper deals with the general basics of the RISC-V architecture and its modularity. Then the special challenges of developing security-critical embedded systems are discussed. Finally, a demo implementation is presented.

Click here for the whitepaper!