News from the community

Vortrag „Post-Quantum Secure Boot mit hashbasierten Signaturen“

Alexander Wagner (Fraunhofer AISEC) hat am 19. Deutschen IT-Sicherheitskongress, veranstaltet vom Bundesamt für Sicherheit in der Informationstechnik (BSI), über die Absicherung von Bootprozessen eingebetteter Systeme mit Post-Quanten-Kryptografie referiert. In seinem Vortrag „Post-Quantum Secure Boot mit hashbasierten Signaturen“ gibt er einen Überblick über hashbasierte…

ASPECT Study "RISC-V Ecosystem"

Analysis of the status and potential of open chip development. In the BMBF-funded ASPECT project, the RISC-V architecture and open hardware approaches in general were examined in the 2nd half of the year for the status, development potential and obstacles of their development ecosystem in Germany. The project was coordinated...

VE-SAFE: Survey on the state of hardware security in Germany in 2021 and requirements for separate protection electronics

As part of the VE-SAFE project, HTV conducted an online survey among manufacturers of electronic devices from Aug. 13, 2021, to Nov. 12, 2021, to assess the state of hardware security in Germany in 2021 and to identify user requirements for the hardware...

RISC-V Prozessor Core for Functional Safety

RISC-V is an open instruction set architecture (ISA) based on the Reduced Instruction Set Computer (RISC) design principle. The greatest strengths of the architecture lie in the modularity of the standard instruction set extensions and the associated possibility of developing very application-specific, high-performance and energy-efficient processors....

Project "SAFE" - funded by the Federal Ministry of Education and Research Germany: Survey on hardware security

Tragen Sie dazu bei, das aktuelle Sicherheitsniveau im Bereich der Hardwaresicherheit im Detail zu erfassen und zu optimieren. Im Rahmen des Verbundprojektes „Verhinderung von Angriffen auf Elektroniksysteme durch innovative Multi-Sensorik“ (VE-SAFE) führt HTV eine Befragung von Herstellern elektronischer Geräte durch,…