Glossar

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A
Ageing
Over the lifetime of a PUF, the material is subject to irreversible ageing effects that can affect the PUF responses and thus the reliability of the PUF.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Analysis
Methods that contribute to verify that the component, module or system complies in functionality, design and robustness to the specification.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Analysis Methods
Methods applied in a laboratory for test and/or analysis to obtain an electrical and/or physical testimony of the investigated device.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Attack Resilience
Ability of a security device to protect its secrets in particular the cryptographic keys or locking bits from readout or modification by means of electrical, optical or mechanical nanoprobing or any kind of signal injection.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
B
BSOI-Wafer
A “Bonded Silicon on Insulator” wafer substrate is a wafer stack where at least two wafers are bonded together, e.g. separated by a silicon layer. These substrates are the basis for various MEMS products.

Contact:
Fritz Herrmann, Fraunhofer IPMS
Bias
Bias describes an imperfection of a PUF that different symbols in PUF responses occur with different probabilities.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162

C
Certification
Conducting a check on whether persons, institutions, processes, products, or services are in compliance with certain criteria, typically done by an independent third party.

Contact:
André Lange, Fraunhofer IIS/EAS

+49 351 45691-220
Classes of Trust – Vertrauensklassen (COT)
Describe the level of trust that is required by a certain class of application and guaranteed throughout the full supply chain. They are under development and proposed to complement the EAL-Classes of the Common Criteria system of  certified security products.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Clock and voltage glitching
Classic attack technique for resilience testing based on clock or voltage glitching to operate chips outside of its specification to circumvent security checks.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Clock glitching
Insertion of an execution fault by operating a device outside the clock supply specifications. A glitch may for instance manifest itself in erroneous computations or skipped instructions.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Common Criteria (CC)
An international standard for the evaluation of security devices according to ISO/IEC 154 08; Designers, manufacturer and test laboratories must be certified by the certification authority, for Germany the Bundesamt für Informationssicherheit BSI, for a conclusive security target a to be specified Evaluation  Assurance Level EAL.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Common Criteria Recognition Arrangement (CCRA)
Evaluation by competent and independent licensed /certified laboratories or entities.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Correlation
Correlation describes an imperfection of a PUF that symbols of a PUF response affect each other and do not occur completely randomly.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Counterfeit
Fraudulent electronic components, modules or systems that may severely affect security and safety have been extracted from electronic waste and refurbished, overproduced by the original manufacturer, false marked e.g. after failing the end of line test, copied by another manufacturer or even marked but empty packages. Often seen in obsolescent devices no longer produced by the ODM. Multichip modules may contain counterfeit chips. Depending on the source and quality complex analysis may be necessary in order to identify counterfeit electronics. Analysis methods and processes are standardized in SAE AS6171 and IDEA.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Counterfeit Detection
Analysis Methods to identify technology deviations from original devices by non-destructive imaging, material characterization and proofing of unique technology features.

Keywords: counterfeiting, physical inspection, imaging/characterization methods, out of spec devices, recycled devices, cloned devices, tampered devices

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
D
E
E-Beam probing
Electron beam based imaging of nm-scaled IC structures in operation for resilience testing of sub 22nm Technologies.

Keywords: Scanning Electon Microscopy, passive and active voltage contrast, backside sample preparation

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Eddy Current Analysis
Non-destructive measurement of local eddy current to detect hidden devices on PCBs for hardware trojan detection.

Keywords: PCB trojan detection, eddy current

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Electro-magnetic spectral analysis
Non-destructive measurement of local electro-magnetic radiation characteristic to detect hidden functionality for trojan detection.

Keywords: PCB trojan detection, EM spectrum analysis

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Electromagnetic fault injection
Insertion of an execution fault by exposing an integrated circuit to bursts of electromagnetic energy. A fault may for instance manifest itself in bit-flips of memory modules or errors in combinational logic. This is achieved through electromagnetic pulses of up to 500V to induce local faults with a precise timing and including tooling for automated scanning.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Electron Microscopy
High resolution imaging and Xray- elemental composition analysis of device surfaces, interconnect cross sections and IC structures for counterfeit analysis.

Keywords: IC technology, transistor structure, SEM/TEM analysis

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Environmental conditions
Temperature, humidity and other reversible environmental effects can affect the PUF responses and thus the reliability. This can be addressed on circuit and algorithmic level.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Equivalence check
Check on whether a particular design exactly corresponds to its specification or another reference.

Contact:
André Lange, Fraunhofer IIS/EAS

+49 351 45691-220
Error-correcting code
Error-correcting codes from communications engineering are incorporated into the key generation for efficient error correction.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Evaluation Assurance Level (EAL)
One of seven levels 0-7 security devices and all entities including  their design, manufacturing, testing, packaging, personalization must be certified to comply with at least the classified EAL -level. All processes including transportation between entities and storage have to be evaluated by an accredited organization.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
F
Fault injection analysis
Analysis of cryptographic and security related implementations by intentional insertion of faults during execution. Faulty outputs or error messages may reveal (parts of) processed secret data. See also clock/voltage glitching and laser/electromagnetic fault injection.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
G
H
Hardware Trojan
Malicious circuitry reducing the security devices ability to protect its secrets in particular the crypto keys or employed to exfiltrate data or cause any kind of functional fail. Hardware Trojans can be integrated during production either at the mask levels of integrated circuits or as an additional device in a module, a PCB or even a plug of a cable.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Hardware penetration testing
Security evaluation of systems assuming an attacker has physical access. The evaluation often includes studying the PCB architecture and on-board ICs, extracting memory contents, or accessing debug interfaces.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Hardware pentesting
Offensive security analysis and penetration tests of embedded systems for PCB analysis, bus sniffing, fuzzing of debug interfaces, etc. UV-light based circumvention of locking Glitching based circumvention with focus on memory read protection.
#PCB testing#bus sniffing#memory readout#fuzzing of debug interfaces

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Helper Data
Data about a specific PUF instantiation that allows to remove unwanted variation in a PUF response (caused e.g. by noise, changed environmental conditions, and ageing) and derive a stable cryptographic key. It must not leak information about the key.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Heterointegration
Describes a manufacturing approach in which two components are manufactured independently of each other and then combined using suitable joining technology.

Contact:
Fritz Herrmann, Fraunhofer IPMS
Higher Order Alphabet
A finite set of at least three symbols used to represent the PUF response (see also Quantization).

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
I
IDEA-STD-1010B
Standard developed by The Independent Distributors of Electronics Association (IDEA) describing primarily visual  test and analysis methods and procedures for identification of counterfeit electronics. Providing more than 300 full color pictures for reference. Laboratories can obtain accreditation for complying with the standard.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Infrared Microscopy and Spectroscopy
Imaging of device surfaces and fingerprinting of the chemical composition of PCB and packaging materials for counterfeit detection.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
J
K
Key Error Probability
The error probability of the derived cryptographic key plays a key role for the reliability of the system.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
L
Laser fault injection
Insertion of an execution fault by leveraging the photoelectric effect to induce a current at a specific location in an integrated circuit. A fault may for instance manifest itself in bit-flips of memory modules or errors in combinational logic.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Light Emission Microscopy
Imaging of emitted lights from single transistors of integrated circuits to identify security features, readout of memories and fingerprinting for resilience testing and counterfeit analysis.

Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Lightweight Authentication
Class of authentication protocols that do not explicitly require conventional cryptographic primitives, such as hash functions, but rely on specific properties of the used PUF. Exposing a large number of PUF response symbols might facilitate machine learning.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162

Lock-in Thermography
Localization of active functional security structures, memory blocks and PUFs in integrated circuits by microscopic thermal imaging and combined electrical stimulation for resilience testing.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
M
Machine Learning
Machine learning techniques are applied to model and predict the responses of a strong PUF to any challenge with high accuracy from a limited sample of challenge-response pairs. Such a model can be used by an attacker to impersonate the PUF.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Mixed Signal ASIC Design
Service for concept, implementation and manufacturing of application specific integrated circuit. An mixed signal system consists of analog and digital (e.g. RISC-V) components.

Keywords: microelectronic, chip design, sensor system

Contact:
Holger Kappert; Head of Department Smart Sensor Systems; Fraunhofer IMS

https://www.ims.fraunhofer.de/en/Core-Competence/Smart-Sensor-Systems/Integrated-Sensor-Systems.html
Monolithic Integration
Describes a manufacturing approach in which two components to be processed are built on top of each other, i.e. further processing takes place directly on the wafer substrate.

Contact:
Fritz Herrmann, Fraunhofer IPMS
N
O
Optical microscopy
Optical Light Microscopy to investigate deviations in device geometry and surface quality for counterfeit detection.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Original Device Manufacturer (ODM)
Manufacturer of the original electronic component or module.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
P
PUF Instance
Manufacturing a PUF design creates a number of PUF instances, each deviating randomly from the nominal design due to manufacturing variations.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
PUF Primitive
A PUF primitive is the fundamental structure that contains manufacturing variation and creates the PUF response.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Physical Unclonable Function (PUF)
A PUF derives a unique (bit-)pattern from physical manufacturing variation.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Q
Quantization
Analog PUF responses need to be digitized and mapped to a finite alphabet for further key generation. A quantization step maps a (digitized) PUF value from a possibly infinite or semi-infinite range to a symbol from a higher order or binary alphabet. Helper data can be generated to map analog values to the center of quantization intervals to reduce the error probability of quantized values.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
R
RISC-V instruction set architecture (ISA)
Open standard for an microcontroller architecture without license fees. Large ecosystem of hardware and software. Used to build trusted system-on-chips to fulfill safety and security regulations.

Keywords: microcontroller, processor, open source hardware

Contact:
Carsten Rolfes; Program Manager Trusted Electronics; Fraunhofer IMS

www.airisc.de
Resilience Testing
Methods to test security functions of devices by Evaluation of specified functions, Side channel analysis, Functional analysis and fault injection.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Reverse Engineering
Preparation analysis methods and workflows for detection of hardware modifications in comparison to design data or golden devices.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
S
SAE AS6171
Standard developed by the Society for Automotive Engineers SAE describing test and analysis methods and procedures for identification of counterfeit electronics. Laboratories can obtain accreditation for complying with the standard.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Scanning Acoustic Microscopy
Scanning acoustic imaging of packaged devices to identify and localize process and aging related delaminations, cracks and voids for counuterfeit detection.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Security Devices
Electronic components that rely on the implementation of at least one encryption algorithm in order to protect internal, transmitted or received data from unauthorized access or modification.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Security Target (ST)
Describes the security devices and all processes that a certain entity has been evaluated to execute.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-521
Side-channel analysis
Analysis of cryptographic and security related implementations by observing execution properties. For instance, execution time, power consumption, electromagnetic radiation, or resource usage may reveal (parts of) processed secret data.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Silicon PUF
PUF that can be manufactured in standard CMOS processes.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Simulation based Fault injection analysis
Injection of faults into a simulation model in order to study the fault effects and verify the effectiveness of safety mechanisms.

Contact:
Jens Warmuth, Fraunhofer IIS/EAS

+49 351 45691-210
Split Manufacturing
Split manufacturing refers to a manufacturing process in which device production is split into multiple parts and those parts are manufactured at two or more foundries so that the design is secure even if some or all of those foundries are potentially untrustworthy.

Contact:
Fritz Herrmann, Fraunhofer IPMS
Strong PUF
A strong PUF has a challenge-response interface that allows to access a large number of responses from the same physical structure. It can be used for secure key storage as well as lightweight authentication.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Surface-Micromachining
This is the manufacturing process – primarily used in MEMS – in which 2.5-3D structures are used through the use of auxiliary structures, so-called sacrificial layers, during manufacturing, whereby these auxiliary structures are finally removed so that spatially free-moving structures are created.

Contact:
Fritz Herrmann, Fraunhofer IPMS
T
Tamper-sensitive PUF
A tamper-sensitive PUF changes its response significantly after a physical tampering event. This change can be observed externally or internally.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
Terahertz-imaging
Imaging in THz electromagnetic spectrum for subsurface imaging of device structures for counterfeit detection.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Thermal imaging analysis
Non-destructive thermal transient imaging and Lock-in Thermography to identify embedded functional chips or deviations in the electrical functionality compared to golden samples for hardware trojan detection on PCB and device level.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Time of flight secondary mass spectroscopy
Lateral resolved chemical imaging, based on time of flight analysis of secondary ions to fingerprint specific material compositions of devices for counterfeit analysis.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Trusted Electronics
Electronic components, modules or systems that have been produced, tested and shipped by the original manufacturer at the are reliably performing only to the specified function for the specified time and combination of environmental conditions and are robust against a specified level of stress or attack.

Contact:
Dr.-Ing. Horst Gieser, Fraunhofer EMFT

+49 89 54759-520
U
T
Voltage glitching
Insertion of an execution fault by operating a device outside the voltage supply specifications. A glitch may for instance manifest itself in erroneous computations or skipped instructions.

Contact:
Dr. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
W
Weak PUF 
A weak PUF only contains a small number of challenge-response pairs. Therefore, its main application is secure key storage.

Contact:
Dr.-Ing. Matthias Hiller, Fraunhofer AISEC

+49 89 3229986-162
X
X-Ray inspection
2D and 3D X-Ray imaging of inner device and PCP structures to identify hardware trojans and counterfeits.

Contact:
Frank Altmann, Fraunhofer IMWS

+49 345 5589-139
Y
Z