"TdvE " at a glance

Agenda

Day 1 - 04.06.2024:

12:00-13:00Registration
13:00-13:25
Welcome address
13:00 – 13:10 Grußwort
Prof. Dr. Amelie Hagelauer / Prof. Dr.-Ing. Georg Sigl
13:10 – 13:25 Grußwort
Prof. Dr. Müller-Groeling
13:25-15:05
Technical/commercial highlights of the ZEUS and ZuSE projects
13:25 – 13:50: VE-ASCOT: Merkmale für eine digitale Identität
Ralf Fust, WIBU Systems
13:50 – 14:15: VE-VIDES: Formal Verification Tools for the Trustworthiness of RTL
Jörg Bormann, Siemens EDA
14:15 – 14:40: VE-Silhouette: Electro-optical co-integration platform for high-density hybrid system
David Weyers, TU Dresden
14:40 – 15:05: VE-HEP: Gehärtete Wertschöpfungsketten mit Open-Source Hardware
Prof. Dr. Steffen Reith, HSRM und Dr. Arnd Weber
15:05-15:55Coffee break and poster session
15:55-16:25
Politics and funding bodies
15:55 – 16:10: Ministerialdirigent Dr. Engelbert Beyer
Link to the German Federal Ministry of Education
16:10 – 16:25: Staatssekretär Tobias Gotthardt
Bayerisches Staatsministerium für Wirtschaft, Landesentwicklung und Energie
16:25-17:30Short presentation of ZEUS and ZuSE results: Poster Pitches
17:30-18:00Coffee break and poster session
18:00-18:30
Consistency and standardization
18:00 – 18:15: Standardisierung
Herr Rüddenklau, IFX
18:15 – 18:30: Konzept Verstetigung VDE Fachgruppe
Prof. Dr.-Ing. Georg Sigl 
18:30-19:00Way to evening event
19:00-22:00Dinner Augustiner Bräustuben (Adresse).  

Directions to dinner on day 1:

The Augustiner Bräustuben (Landsberger Str. 19, 80339 Munich) is just under 30 minutes' walk from the venue. There is also the U5 subway (17 minutes). Route on Google Maps

Day 2 – 05.06.2024

09:00-09:45
Welcome and keynote
09:00 – 09:10 Begrüßung
Dr.-Ing. Horst Gieser
09:10 – 09:45 Keynote: Chiplets are the next key innovation for the open source hardware community
Thorsten Grawunder, Swissbit AG
09:45-10:15The Velektronik project: Spotlights
10:15-10:45Coffee break and poster exhibition
10:45-12:00Analysis and manufacturing workshop (parallel)

Analysis
Moderation: Dr.-Ing. Horst Gieser
10:45-11:10 VE-CeraTrust: Verhinderung von Angriffen auf Elektroniksysteme durch neuartige keramische Mehrlagensysteme
Dr.-Ing. Uwe Krieger, VIA electronic GmbH
11:10-11:35 VE-FIDES: Towards a Comprehensive System for Physical Hardware Inspection for Trust
Bernhard Lippmann, Infineon Technologies AG
11:35-12:00 VE-HEP: Security Analysis of Locked Scan Chains with Failure Analysis Tools
Lars Renkes, Technische Universität Berlin
Manufacturing
Moderation: Prof. Dr.-Ing Wolfgang Heinrich
10:45-11:05 Micro-Transfer Printing: A Technology supporting D2W Integration for Distributed Manufacturing
Dr. Tino Jäger, X-FAB MEMS Foundry GmbH
11:05-11:25 Velektronik: Hetero-Integration von III-V-Chiplets mit BiCMOS für mm-Wellen-Systeme – technische Lösung und Vertrauenswürdigkeit
Prof. Dr.-Ing Wolfgang Heinrich, Ferdinand-Braun-Institut
11:25-11:45 T4T: Vertrauenswürdige Elektronik in verteilter Fertigung
Sascha Bönhardt, Fraunhofer-Institut für Photonische Mikrosysteme IPMS
11:45-12:00 Q&A
12:00-13:15Lunch
13:15-14:55
Design Workshop
Moderation: Dr. Roland Jancke
13:15-13:35 VE-DIVA-IC: Formal Verification of Security Properties on RISC-V Processors
Dr. Christian Appold, DENSO AUTOMOTIVE Deutschland GmbH
13:35-13:55 VE-DIVA-IC: Mixed Signal RISC-V ASIC with Transaction Monitoring
Carsten Rolfes, Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS und Martin Flasskamp, Universität Bielefeld
13:55-14:15 VE-DIVA-IC: Semiconductor-based Quantum Random Number Generator
Dr. Christian Lammers, Elmos Semiconductor SE
14:15-14:35 VE-SensIC: Tamper-proof cryptographic keys generation for identification and authentication
Shawon Alam, Karlsruhe Institute of Technology und Wacime Hadrich, Hochschule Offenburg
14:35-14:55 VE-VIDES: Verification of trustworthiness with formal and AI methods
Prof. Dr. Djones Lettnin, Infineon Technologies AG
14:55-15:00Conclusion and outlook