{"id":8773,"date":"2024-05-24T15:29:00","date_gmt":"2024-05-24T13:29:00","guid":{"rendered":"https:\/\/www.velektronik.de\/?page_id=8773"},"modified":"2024-06-26T14:12:46","modified_gmt":"2024-06-26T12:12:46","slug":"tdve","status":"publish","type":"page","link":"https:\/\/www.velektronik.de\/en\/tdve\/","title":{"rendered":"\"TdvE \" at a glance"},"content":{"rendered":"

<\/p>\n\n\n\n

Agenda<\/h2>\n\n\n\n

Day 1 - 04.06.2024:<\/h3>\n\n\n\n
12:00-13:00<\/td>Registration<\/mark><\/td><\/tr>
13:00-13:25<\/td>
<\/span>Welcome address<\/div>
13:00 \u2013 13:10 Gru\u00dfwort<\/strong><\/mark>
Prof. Dr. Amelie Hagelauer \/ Prof. Dr.-Ing. Georg Sigl<\/em><\/mark>
13:10 \u2013 13:25 Gru\u00dfwort<\/mark><\/strong>
Prof. Dr. M\u00fcller-Groeling<\/em><\/mark><\/div><\/div><\/td><\/tr>
13:25-15:05<\/td>
<\/span>Technical\/commercial highlights of the ZEUS and ZuSE projects<\/div>
13:25 \u2013 13:50: VE-ASCOT: Merkmale f\u00fcr eine digitale Identit\u00e4t<\/mark><\/strong>
Ralf Fust, WIBU Systems<\/em><\/mark>
13:50 \u2013 14:15: VE-VIDES: Formal Verification Tools for the Trustworthiness of RTL<\/mark><\/strong>
J\u00f6rg<\/em> Bormann, Siemens EDA<\/em><\/mark>
14:15 \u2013 14:40: VE-Silhouette: Electro-optical co-integration platform for high-density hybrid system<\/mark><\/strong>
David Weyers, TU Dresden<\/em><\/mark>
14:40 \u2013 15:05: VE-HEP: Geh\u00e4rtete Wertsch\u00f6pfungsketten mit Open-Source Hardware<\/mark><\/strong>
Prof. Dr. Steffen Reith, HSRM und Dr. Arnd Weber<\/em><\/mark><\/div><\/div><\/td><\/tr>
15:05-15:55<\/td>Coffee break and poster session<\/mark><\/td><\/tr>
15:55-16:25<\/td>
<\/span>Politics and funding bodies<\/div>
15:55 \u2013 16:10: Ministerialdirigent Dr. Engelbert Beyer<\/mark><\/strong>
To the German Federal Ministry of Education<\/em>
<\/mark>16:10 \u2013 16:25: Staatssekret\u00e4r Tobias Gotthardt<\/mark><\/strong>
Bayerisches Staatsministerium f\u00fcr Wirtschaft, Landesentwicklung und Energie<\/em><\/mark><\/div><\/div><\/td><\/tr>
16:25-17:30<\/td>Short presentation of ZEUS and ZuSE results: Poster Pitches<\/mark><\/td><\/tr>
17:30-18:00<\/td>Coffee break and poster session<\/mark><\/td><\/tr>
18:00-18:30<\/td>
<\/span>Consistency and standardization<\/div>
18:00 \u2013 18:15: Standardisierung<\/mark><\/strong>
Herr R\u00fcddenklau, IFX<\/em><\/mark>
18:15 \u2013 18:30: Konzept Verstetigung VDE Fachgruppe<\/strong> <\/mark>
Prof. Dr.-Ing. Georg Sigl<\/em> <\/mark><\/div><\/div><\/td><\/tr>
18:30-19:00<\/td>Way to evening event<\/mark><\/td><\/tr>
19:00-22:00<\/td>Dinner Augustiner Br\u00e4ustuben (Adresse<\/a>). <\/em> <\/mark><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Directions to dinner on day 1:<\/h3>\n\n\n\n

The Augustiner Br\u00e4ustuben (Landsberger Str. 19, 80339 Munich) is just under 30 minutes' walk from the venue. There is also the U5 subway (17 minutes). Route on Google Maps<\/a><\/p>\n\n\n\n

Day 2 \u2013 05.06.2024<\/h3>\n\n\n\n
09:00-09:45<\/td>
<\/span>Welcome and keynote<\/div>
09:00 \u2013 09:10 Begr\u00fc\u00dfung<\/mark><\/strong>
Dr.-Ing. Horst Gieser<\/em>
<\/mark>09:10 \u2013 09:45<\/strong> Keynote: Chiplets are the next key innovation for the open source hardware community<\/strong><\/mark>
Thorsten Grawunder, Swissbit AG<\/em><\/mark><\/div><\/div><\/td><\/tr>
09:45-10:15<\/td>The Velektronik project: Spotlights<\/mark><\/td><\/tr>
10:15-10:45<\/td>Coffee break and poster exhibition<\/mark><\/td><\/tr>
10:45-12:00<\/td>Analysis and manufacturing workshop (parallel)<\/mark>

<\/span>Analysis <\/div>
Moderation: Dr.-Ing. Horst Gieser<\/em>
<\/mark>10:45-11:10<\/strong> VE-CeraTrust: Verhinderung von Angriffen auf Elektroniksysteme durch neuartige keramische Mehrlagensysteme<\/strong><\/mark>
Dr.-Ing. Uwe Krieger, VIA electronic GmbH<\/em>
<\/mark>11:10-11:35<\/strong> VE-FIDES: Towards a Comprehensive System for Physical Hardware Inspection for Trust<\/strong><\/mark>
Bernhard Lippmann, Infineon Technologies AG<\/em>
<\/mark>11:35-12:00<\/strong> VE-HEP: Security Analysis of Locked Scan Chains with Failure Analysis Tools<\/strong><\/mark>
Lars Renkes, Technische Universit\u00e4t Berlin<\/em><\/mark><\/div><\/div>
<\/span>Manufacturing<\/div>
Moderation: Prof. Dr.-Ing Wolfgang Heinrich<\/mark><\/em>
<\/mark>10:45-11:05 Micro-Transfer Printing: A Technology supporting D2W Integration for Distributed Manufacturing<\/mark><\/strong>
Dr. Tino J\u00e4ger, X-FAB MEMS Foundry GmbH<\/em>
<\/mark>11:05-11:25 Velektronik: Hetero-Integration von III-V-Chiplets mit BiCMOS f\u00fcr mm-Wellen-Systeme \u2013 technische L\u00f6sung und Vertrauensw\u00fcrdigkeit<\/mark><\/strong>
Prof. Dr.-Ing Wolfgang Heinrich, Ferdinand-Braun-Institut<\/em>
<\/mark>11:25-11:45<\/strong> T4T: Vertrauensw\u00fcrdige Elektronik in verteilter Fertigung<\/strong><\/mark>
Sascha B\u00f6nhardt, Fraunhofer-Institut f\u00fcr Photonische Mikrosysteme IPMS<\/em>
<\/mark>11:45-12:00 Q&A<\/mark> <\/strong><\/div><\/div><\/td><\/tr>
12:00-13:15<\/td>Lunch<\/mark><\/td><\/tr>
13:15-14:55<\/td>
<\/span>Design Workshop<\/div>
Moderation: Dr. Roland Jancke<\/em><\/mark>
13:15-13:35 VE-DIVA-IC: Formal Verification of Security Properties on RISC-V Processors<\/mark><\/strong>
Dr. Christian Appold, DENSO AUTOMOTIVE Deutschland GmbH<\/em><\/mark>
13:35-13:55 VE-DIVA-IC: Mixed Signal RISC-V ASIC with Transaction Monitoring<\/strong><\/mark>
Carsten Rolfes, Fraunhofer-Institut f\u00fcr Mikroelektronische Schaltungen und Systeme IMS und Martin Flasskamp, Universit\u00e4t Bielefeld<\/em><\/mark>
13:55-14:15 VE-DIVA-IC: Semiconductor-based Quantum Random Number Generator<\/mark><\/strong>
Dr. Christian Lammers, Elmos Semiconductor SE<\/em><\/mark>
14:15-14:35 VE-SensIC: Tamper-proof cryptographic keys generation for identification and authentication<\/strong><\/mark>
Shawon Alam, Karlsruhe Institute of Technology und Wacime Hadrich, Hochschule Offenburg<\/em><\/mark>
14:35-14:55<\/strong> VE-VIDES: Verification of trustworthiness with formal and AI methods<\/strong><\/mark>
Prof. Dr. Djones Lettnin, Infineon Technologies AG<\/em><\/mark><\/div><\/div><\/td><\/tr>
14:55-15:00<\/td>Conclusion and outlook<\/mark><\/td><\/tr><\/tbody><\/table><\/figure>","protected":false},"excerpt":{"rendered":"

Agenda Tag 1 \u2013 04.06.2024: 12:00-13:00 Registrierung 13:00-13:25 13:25-15:05 15:05-15:55 Kaffeepause und Poster Session 15:55-16:25 16:25-17:30 Kurzvorstellung der ZEUS und ZuSE Ergebnisse: Poster Pitches 17:30-18:00 Kaffeepause und Poster Session 18:00-18:30 18:30-19:00 Weg zur Abendveranstaltung 19:00-22:00 Dinner Augustiner Br\u00e4ustuben (Adresse).   Wegbeschreibung…<\/p>","protected":false},"author":10,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-8773","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"\nTdvE auf einen Blick<\/title>\n<meta name=\"description\" content=\"Erfahren Sie mehr \u00fcber die Agenda f\u00fcr den Tag der vertrauensw\u00fcrdigen Elektronik. \u2713 Networking \u2713 Vortr\u00e4ge \u2713 Diskussionen\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, 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